A programmable logic device (PLD) is designed to be user-programmable so that users may implement logic designs of their choices. One type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to that used in a Programmable Logic Array (PLA) or a Programmable Array Logic (PAL) device. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream, typically from off-chip memory, into configuration memory cells of the FPGA. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
PLDs also have different “modes” depending on the operations being performed on them. A specific protocol allows a programmable logic device to enter into the appropriate mode. Typical PLDs have internal blocks of configuration memory which specify how each of the programmable cells will emulate the user's logic. During a “program” mode, a configuration bitstream is provided to non-volatile memory, such as a read-only memory (ROM) (e.g. a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM)) either external or internal to the programmable logic device. Each address is typically accessed by specifying its row and column addresses. During system power up of a “startup” mode, the configuration bits are successively loaded from the non-volatile memory into static random access memory (SRAM) configuration latches of a configuration logic block. At the end of this start-up phase, the PLD is now specialized to the user's design, and the PLD enters into “user” mode as part of its normal operation.
Currently, the FPGA configuration is checked with a cyclic redudancy check (CRC) register. As configuration data is loaded into the FPGA, that data is accumulated into a CRC register, which in turn generates a “signature” of the data. At any point in the incoming configuration bitstream, typically near the end, the expected signature can be loaded into the CRC and compared with the generated signature to determine whether they match. If they do not, then the configuration process will halt, and a signal will be output to indicate an error. Also, an identification (ID) code of a device is shifted in as part of the configuration bitstream. It is compared with a hard-wired ID code to see if the ID code of the device and the incoming bitstream match. If they do not, then the configuration process will halt, and an error signal will be output. If either the ID code or the CRC is incorrect, a board designer must interpret the error and manually issue a configuration reset and restart the configuration process.
However, the CRC and ID code checking process of a conventional device has a number of shortcomings. For example, if a CRC error or some other error associated with the incoming data is detected in a conventional device, the conventional device halts the configuration process. Further, if the CRC check command is not issued, then the CRC is not checked at the end of the bitstream. Therefore, a conventional device will startup anyway, regardless of whether there are errors in the bitstream. There is also a problem if the CRC check command itself is garbled. In that case, then the CRC is not checked at the end of the bitstream, and the FPGA will startup even if there are errors in the bitstream. Further, if there are any commands in the bitstream (e.g. a Desynch command, also commonly called a start-up command) after the CRC check command that is garbled, then the device may not startup even if the CRC was checked and it passed the check. Finally, the SRAM of a conventional device should be checked to determine if it was loaded correctly.
Accordingly, there is a need for an improved circuit for and method of validating a bitstream loaded into a programmable logic device.